The present invention relates to integrated circuits and methods of manufacturing integrated circuits. More particularly, the present invention relates to a method of manufacturing integrated circuits having transistors with shallow source/drain extension regions.
Integrated circuits (ICs), such as, ultra-large scale integrated (ULSI) circuits, can include as many as one million transistors or more. The ULSI circuit often include complementary metal oxide semiconductor (CMOS) field effect transistors (FETS). The transistors can include semiconductor gates disposed between drain and source regions. The drain and source regions are typically heavily doped with a P-type dopant (boron) or an N-type dopant (phosphorous).
The drain and source regions generally include a thin extension that is disposed partially underneath the gate to enhance the transistor performance. Shallow source and drain extensions help to achieve immunity to short-channel effects which degrade transistor performance for both N-channel and P-channel transistors. Short-channel effects can cause threshold voltage roll-off and drain-induced barrier lowering. Both drain-induced barrier lowering and threshold voltage roll-off increases random process variation and degrades the robustness of the transistor. Shallow source and drain extensions and, hence, controlling short-channel effects, are particularly important as transistors become smaller.
Traditionally, source and drain regions along with shallow source and drain extensions are formed by a double implant process. In the double implant process, shallow source and drain extensions are formed by providing a transistor gate structure without sidewall spacers on a top surface of a silicon substrate. Next, an ion implantation process is used to dope the silicon substrate on both sides of the gate structure. Without the sidewall spacers on the gate structure, the implantation process introduces dopants into a thin region just below the top surface of the substrate to form the drain and source extensions. During formation of the source and drain extensions, the source and drain regions are also partially formed.
After the source and drain extensions are formed, insulating spacers, which abut lateral sides of the gate structure, are provided over the source and drain extensions. Next, a second implantation step is performed to form the deeper source and drain regions. The source and drain extensions are not further doped due to the blocking capability of the silicon dioxide spacers. Following formation of the source and drain regions and the source and drain extensions, a high-temperature thermal anneal is performed to activate dopants implanted in the regions.
Using ion implantation to form regions within a semiconductor substrate results in the following disadvantages: (1) dopant tail diffusion through the crystal lattice which causes short channel effects, (2) damage to the crystalline lattice caused by injecting high energy ions, and (3) inability to form ultra-shallow implant regions due to the limits of the implant mechanism. Damage to the crystalline lattice structure allows dopant to rapidly diffuse throughout the lattice. The disadvantages of ion implantation negatively effect proper formation of shallow source and drain extension regions. Further, the negative impact of ion implantation becomes more pronounced as dimension of the source and drain extensions are reduced to facilitate smaller transistor sizes. For example, the limited ability of implant mechanisms to perform low energy implants (e.g., less than 1 KeV) for most commonly used dopants such as Arsenic (As) and Boron (B) makes formation of shallow regions very difficult and highly variable. Rapid diffusion increases process variation and reduces transistor functionality.
Thus, a method of forming shallow source and drain extensions without ion implantation is needed. Further, there is a need for an efficient method of forming source and drain extension regions. Even further still, there is a need for transistors including shallow source and drain extensions with minimal crystal damage.
The present invention relates to a method of manufacturing an integrated circuit. The integrated circuit includes a gate structure between a source region and a drain region in a semiconductor substrate. The method includes providing a doped material adjacent to the gate structure and above the semiconductor substrate. Further, the method includes annealing the integrated circuit causing dopants in the doped material to diffuse into the semiconductor substrate forming an extension region.
The present invention further relates to a method of manufacturing an ultra-large scale integrated circuit including a plurality of field effect transistors having source and drain extension regions. The method includes steps of forming at least part of a gate structure on a top surface of a semiconductor substrate and between a source and a drain. The method further includes forming a protective spacer material abutting a wall of the gate structure. In addition, the method includes forming a doped material abutting the protective spacer and forming a second spacer material abutting the doped material, whereby the doped material is between the protective spacer material and the second spacer material. The method also includes doping the source and drain regions in the semiconductor material. In addition, the method includes annealing the integrated circuit to cause dopants from the doped material and dopants from the source and drain regions to diffuse and form extension regions.
The present invention also relates to an integrated circuit including a transistor. The transistor has a gate structure on a top surface of a semiconductor substrate and is disposed between a source and a drain. The transistor includes a source extension region and a drain extension region. Advantageously, the source and drain extension regions do not exhibit channeling effect or crystal damage from dopant implant.